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INTEGRATED CIRCUITS
DATA SHEET
PCF5077T Power amplifier controller for GSM and PCN systems
Preliminary specification File under Integrated Circuits, IC17 1997 Nov 19
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
FEATURES * CMOS low-voltage, low-power * Can be used in burst mode with power-down * 3-wire serial bus interface with the bus available in Power-down mode * On-chip ramp generator for 256 different power levels with two dynamic ranges * Two programmable regulator start conditions (VKICK and VHOME) * Programmable analog output voltage limitation * Ramping speed depending on the 13 MHz system frequency clock for Global System for Mobile communications (GSM) and Personal Communications Network (PCN) * Low swing input buffer for the 13 MHz master clock * Compatible to a large number of different RF power modules QUICK REFERENCE DATA SYMBOL VDDD VDDA1 VDDA2 IDD(oper)(tot) Tamb Notes PARAMETER digital supply voltage analog supply voltage 1 analog supply voltage 2 (for OP4) total operating current on the VDD pins operating ambient temperature note 2 CONDITIONS note 1 note 1 MIN. 2.7 2.7 2.7 - -40 TYP. 3.0 3.0 5.0 9 -
PCF5077T
* Programmable temperature matching * Dual supply concept for analog and digital part * No external filter for suppression of clock pulse feed through * Direct power control with ramping function (control loop can be switched off) * On-chip Power-on reset for all registers * Serial bus is compatible to bus systems independent of additional clock pulse after rising edge of strobe signal * Low operating current consumption * TTL compatible interface * Programmable gain factor for sensor signal at OP1 * Two different voltages for 1 LSB of the burst power Digital-to-Analog Converter (DAC) are programmable.
MAX. 6.0 6.0 6.0 18 +85
UNIT V V V mA C
1. The voltages VDDA1 and VDDD must be equal and VDDA2 must be either equal or greater than VDDA1 = VDDD. 2. VDDA1 = VDDD = 3 V and VDDA2 = 5 V. The VDD pins are: VDDA1, VDDA2 and VDDD. ORDERING INFORMATION TYPE NUMBER PCF5077T PACKAGE NAME SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm VERSION SOT369-1
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
BLOCK DIAGRAM
PCF5077T
handbook, full pagewidth
RF input (sensor)
C2
voltage control for RF power module D1 R1 C1 VS 1 RF-ZERO + DC C6 BVS 4 VINT(N) 15 VINT(O) 14
VD1
BAND GAP VDDA1 Ibias Vref 8 DAC8 DACA QRSA -0.8 100 mV DACA POWER LEVEL REGISTER 8-bit KICKA VKICK REGISTER VHOME REGISTER LIMITER REGISTER DF0/1, DC, DR0/1, TEST 6-bit 6 + 2-bit 2-bit 6 -0.33 +0.33 SC-ADDER KICKA QRSA Vref 30 A C4 10 pF R2 1 k
4.8 pF C5 19.2 pF R3 OP1 3.5 k Vref DR1 R4 8.4 k HPA + DC
DR0 HPA R5 5 k Vref
OP4
SLOPE GENERATOR
ANALOG FILTER Vref
R8 2.8 k
R9 2.8 k
COMPARATOR
R10 DAC6 4.2 k
HPA + DC
INPUT BUFFER
PCF5077T
SERIAL BUS INTERFACE
1/6
CONTROL
2 DF
9 STROBE
10 CLK
11 DATA
13 VSSA
12
3
16
6 VDDD
8 CLK13
5 TRIG
7
MGK910
VDDA1 VSSD VDDA2
PD
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PINNING SYMBOL VS DF VDDA1 BVS TRIG VDDD PD CLK13 STROBE CLK DATA VSSD VSSA VINT(O) VINT(N) VDDA2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION sensor signal input programmable 3-state output analog supply voltage 1 buffered sensor signal output trigger signal input digital supply voltage power-down input (active LOW) 13 MHz master clock input (low-swing) serial bus strobe signal input serial bus clock signal input serial bus data signal input digital ground analog ground integrator output integrator inverting input analog supply voltage 2 (for OP4)
handbook, halfpage
PCF5077T
VS 1 DF 2 VDDA1 3 BVS 4
16 VDDA2 15 VINT(N) 14 VINT(O)
PCF5077T
TRIG 5 VDDD 6 PD 7 CLK13 8
MGK909
13 VSSA 12 VSSD 11 DATA 10 CLK 9 STROBE
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION General This CMOS device integrates operational amplifiers, two digital-to-analog converters and a serial bus interface to implement an `Integrating-Controller' (see Fig.1). It is designed to control both the power level and the up- and down-ramping of GSM/PCN transmit bursts. The GSM/PCN power-up and power-down ramping curves are generated on-chip, using an internal clock frequency of 1 2.166 MHz T cy = ------ , that is generated internally by f clk dividing the external 13 MHz clock signal by six. Generally, the power amplifier is ramped-up after a rising edge on pin TRIG and ramped-down after a falling edge. The content of the power level register (bits PL7 to PL0) determines which of the 2 x 256 possible values the top of the burst will have. To match the controller to different power modules and sensors several parameters must be adapted. The following parameters influence the performance of the transmission system: * The external capacitor C1 in Fig.1 determines the maximum bandwidth of the power control loop, 1997 Nov 19 4
depending on the highest steepness of the control curve of the power module and on the sensor attenuation. * The maximum output voltage at pin VINT(O) to protect the power module: the limiting value of VINT(O) can be set to 4, 3.3 or 2.55 V, depending on the contents of the limiter register (bits Lim1 and Lim0). This limiting results in a ringing at VINT(O) (typ. 200 mV peak-to-peak value) but it will not be transferred to the antenna because the power module is in saturation. The limiter register bits Lim1 and Lim0 can be used to switch off the limiter option (see Table 5). * The home position at VINT(O): the integrator output voltage at home position (PD = HIGH and TRIG = LOW) is programmed by means of the VHOME register. Bits Vh5 to Vh0 are fed into a 6-bit DAC that generates a part of VHOME. * The temperature behaviour of the home position: bits DVh1 and DVh0 can be used to compensate temperature dependencies (-2 or -4 mV/K) of the control curves of the power module. This completes the setting of VHOME. * The KICK voltage: the 6 bits of the VKICK register (Vk5 to Vk0) determine the differential integrator input voltage just after a ramp-up starting signal is detected.
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
The register information is written via a 3-wire serial bus (see Sections "Serial bus programming" and "Data format"). The output of pin DF is for general purpose which can have three different states (LOW, HIGH and 3-state), depending on the values of bits DF0 and DF1 in the serial register. Dual supply pins are provided for the analog and digital blocks. Reset function After switching on the power supply, the on-chip reset is active for maximal 50 s when the rising slope of VDDD has reached 1.5 0.4 V. During this reset, all controllers are set to the home position and the registers are set to their default values. If the supply voltage drops below the reset threshold a constant reset will appear. Operating conditions PD = LOW The serial bus interface is operating, e.g. all registers can be programmed but no effect will be seen on any pin. The contents of the registers are passed to the rest of the circuit only during power-up and with the 13 MHz master clock applied. If the low-swing input buffer at pin CLK13 is switched off, neither the SC-adder nor the slope generator will function. This means that after the chip is powered-up, the outputs have to settle again to the programmed register values. The settling time is dominated by the slow power-up of the band gap of typically 50 s.
PCF5077T
When the chip is used in the burst mode, it is important to switch on the PCF5077T before the power module or the RF power. Otherwise it is possible that a positive spike at VINT(O) will open the power module. A safe value is tON = 200 s between the switching on of the PCF5077T and the switching on of the power module respectively the next TRIG (see Fig.3). PD = HIGH The whole chip is active. CLK13 clocks the internal state machine as well as the SC-adder and slope generator. Every change at TRIG is recognized if the master clock is running. The contents of the serial bus registers are processed. If the master clock is switched off during power-up, the state machine is stopped and the output of the SC-adder and slope generator becomes undefined. Nevertheless, by reactivating the master clock, the output of the SC-adder and slope generator will settle to the old values again. The analog integrating controller The analog integrating controller consists of two operational amplifiers (OP1 and OP4) and a comparator. OP1 amplifies the sensor signal and OP4 is used to form a differential integrator. The comparator is used to limit the integrator output voltage to the value selected by bits Lim1 and Lim0 in the limiter register. A (Schottky) diode D1 as external rectifier is connected to pin VS. The SC-adder block generates the voltage for the ramping of the power module.The differential integrator integrates the difference of this voltage and the voltage detected at the diode. The integrator output voltage VINT(O) is used to control the power amplifier module.
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
Table 1 Definition of some voltages used in Figs 1 and 3 DESCRIPTION reference voltage, typically 1.25 V voltage over the sensor diode D1
PCF5077T
SYMBOL Vref VD1 VPL VVS VBVS VKICK VHOME VQRS VRFIN
voltage determining the power level; it is generated in the Switched Capacitor (SC)-adder block if switch DACA is closed (i.e. if the signal DACA is HIGH) voltage at pin VS when RF is rectified by the sensor diode D1 amplified voltage from pin VS voltage determining the kick level; it is generated in the SC-adder block if switch KICKA is closed (i.e. if the signal KICKA is HIGH) voltage determining the home position voltage; if HPA signal is active, the output of DAC6 plus temperature compensation is amplified and appears at the output of OP4 (pin VINT(O)) low voltage at the output of the SC-adder block which causes a ramp-down with a shortened tail if switch QRSA is closed (i.e. if the signal QRSA is HIGH) input signal to the power amplifier open (HPA + DC is either HPA switch or DC bit). Switch HPA is closed when there is no home position. Due to the negative differential input voltage VKICK, the integrator output will start to rise. After 18Tcy (time C) the output of DAC8 is connected to the SC-adder and slope generator block. The input of the 8-bit DAC comes from bits PL7 to PL0 in the power level register. The slope generator will generate a smooth curve between the former and the new output value of the SC-adder block. The power amplifier is ramped-up via the integrator in approximately 22Tcy. This condition is stable as long as TRIG remains HIGH. Two clock periods after a falling edge at TRIG the ramp-down is started (time E). The SC-adder output voltage will change to VQRS (-100 mV), because DACA becomes inactive and QRSA active. This causes a ramp-down with a shortened tail. The slope generator again generates a smooth curve between the new SC-adder output voltage and the old SC-adder output voltage. The slope generator must have reached its final value at 38Tcy after the recognized falling edge of TRIG because the HPA signal is activated again and by that turning the integrator into its `home position' (time G). The integrator output voltage will be regulated once more to the value defined in the VHOME register.
Ramp generation (see Fig.3) The circuit is activated with the PD signal going HIGH before time mask AS and deactivated after ramping down, e.g. at time GS to HS. For this usual `power-down burst mode' application in GSM/PCN mobile stations, the RF input power at the power module must be activated between time AS and BS (when the home position at VINT(O) has already reached its stable value) and deactivated between time GS and HS. This is necessary for many types of power modules to meet the -70 dB margin. A ramp-up is started by a rising edge of the TRIG signal. The TRIG signal and all other internal signals are delayed by two clock periods (2Tcy) with respect to the signal at pin TRIG. The timing diagram shows a possible relationship between the chip timing (time B to G) relative to the GSM-mask (AS to HS). However, the user is free to choose the rising and falling edge of TRIG independently so that the mask is not violated. DESCRIPTION OF THE SIGNALS STARTING AT A STABLE HOME VINT(O) AT TIME B - 2Tcy
POSITION OF
The integrator output voltage is regulated to the value defined in the VHOME register. The output of the slope generator is connected to the negative input VINT(N) of operational amplifier OP4 (VKICK is defined by bits Vk5 to Vk0 in the VKICK register). Two clock periods after a rising edge on pin TRIG, the integrator start condition circuitry is turned off and OP4 is switched into an integrator configuration (time B). The HPA switches will 1997 Nov 19 6
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PCF5077T
handbook, full pagewidth
AS
22Tcy
BS
18Tcy
CS
22Tcy
DS
ES
22Tcy
FS
18Tcy
GS
22Tcy
HS
dB 4 1 1 6
t1
(8Tcy)
30
70
B 2Tcy tON 200 s
18Tcy
C
,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,,
t2 E 2Tcy tOFF
(2Tcy)
38Tcy 44Tcy
G
TRIG PD KICKA
HPA QRSA DACA RFIN
(7)
RF-ZERO
(1) (3) (4) (5) (2) (6)
MGK912
(1) (2) (3) (4) (5) (6) (7)
tRFON = tON - 12Tcy to tON + 2Tcy. tRFOFF = 44Tcy to 66Tcy. VKICK (start integrator) applied to integrator. VPL applied to integrator. VQRS applied to integrator. VHOME at output of OP4. This timing of the RF input power (from the power module) ensures that the -70 dB margin is met, even if the isolation of the power module is bad.
Fig.3 Timing diagram of a typical ramp-up/ramp-down curve.
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
Serial bus programming A simple 3-wire unidirectional serial bus is used to program the circuit. The 3 wires are DATA, CLK and STROBE. The data sent to the device is loaded in bursts framed by STROBE. Programming clock edges and their appropriate data bits are ignored until STROBE goes active LOW. The last four address bits are decoded on the active STROBE edge. This produces an internal load pulse to store the data in one of the addressed registers. To avoid erroneous circuit operation, the STROBE pulse is not allowed during internal data reads by the rest of the circuit. This condition is guaranteed by respecting a minimum STROBE pulse width after data transfer. Only the last 16 bits serially clocked into the device are retained within the programming register. Additional Table 2 Programming register format DATA BITS SUBADDRESS MSB p15 data9 Table 3 p14 to p8 data8 to data2 Register bit allocation DATA FIELD (D9 TO D0) SUBADDRESS MSB p15 Vk5 Vh5 PL7 Table 4 p14 Vk4 Vh4 PL6 p13 Vk3 Vh3 PL5 p12 Vk2 Vh2 PL4 p11 Vk1 Vh1 PL3 p10 Vk0 Vh0 PL2 p9 Lim1 PL1 p8 Lim0 PL0 p7 DC DR1 DF1 LSB p6 Test DR0 DF0 p5 0 0 1 p4 0 1 1 p3 1 1 1 p7 data1 LSB p6 data0 p5 Sadd1 p4 Sadd0 p3 add3 p2 add2
PCF5077T
leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. The bus is also programmable during power-down. Data format Data is entered with the most significant bit (MSB) first. The leading 10 bits p15 to p6 are the data field, the following bits p5 and p4 form the subaddress, while the last 4 bits p3 to p0 are the device address field. The PCF5077T uses only one of the available addresses. The format is given in Table 2. The correspondence between data and address fields is given in Table 3 and the description in Table 4. All three registers in Table 3 are set to 00H during reset.
DEVICE ADDRESS p1 add1 p0 add0
DEVICE ADDRESS p2 0 0 0 p1 1 1 1 p0 0 0 0
DVh1 DVh0
Description of bits used in Table 3 BITS DESCRIPTION 6 bits to control the kick voltage in 64 steps 6 bits to control the home position voltage in 64 steps 8 bits to control the power level in 256 steps 2 bits to control the limiter voltage (see Table 5) direct control with ramping function (control loop is switched off when DC = 1) test mode (Test = 1); must always be set to logic 0 in application 2 bits to set the temperature coefficient of VHOME (see Table 6) gain factor of OP1 gain factor for slope generator output enable of the 3-state output on pin DF (for DF1 = 0, pin DF is in 3-state mode) data output on pin DF 8
Vk5 to Vk0 Vh5 to Vh0 PL7 to PL0 Lim1 and Lim0 DC Test DVh1 and DVh0 DR1 DR0 DF1 DF0 1997 Nov 19
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
Table 5 Lim1 0 0 1 1 Table 6 Limiter voltage Lim0 0 1 0 1 LIMITER VOLTAGE (V) limiter off 4.00 3.30 2.55 TOLERANCE AT Tamb = 27 C (mV) - 250 250 250
PCF5077T
TOLERANCE AT Tamb = 85 C (mV) - 350 350 350
Programmable temperature coefficient of VHOME DVh1 0 0 1 1 DVh0 0 1 0 1 VHOME(1) Vh 0.4 mV/K Vh - 2 mV/K 20% Vh - 4 mV/K 20% VSS
Note 1. Vh = voltage programmed in VHOME register bits Vh5 to Vh0 and generated by DAC6. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA1 VDDA2 VDDD VI VI(VS) II(n) Ptot Tstg Tamb Note 1. Pulses of 7 V are allowed for less than 100 ms. PARAMETER analog supply voltage 1 analog supply voltage 2 digital supply voltage DC input voltage on all pins (except pin VS) DC input voltage on pin VS DC input current on any signal pin total power dissipation storage temperature operating ambient temperature MIN. -0.5 -0.5 -0.5 -0.5 -3.0 -10 - -65 -40 MAX. +6.0(1) +6.0(1) +6.0(1) VDD + 0.5 VDD + 0.5 +10 83 +150 +85 V V V V V mA mW C C UNIT
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PCF5077T
OPERATING CHARACTERISTICS VDDA1, VDDA2 and VDDD = VDD = 2.7 to 6.0 V; VDDD = VDDA1 VDDA2; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Operational amplifier (OP1) VDDA1 GB Gmin Gmax Voffset VDDA2 GB PSRR SRpos SRneg Voffset Vo(min) Vo(max) Io analog supply voltage 1 gain bandwidth product minimum gain maximum gain offset voltage VDDA1 = 3.0 V DR1 = 0 DR1 = 1 no load at output 2.7 2.0 -8.1 5.9 -20 3.0 - -7.6 6.4 0 6.0 - -7.1 6.9 +20 6(1) - - - - +20 0.3 - - 10 1 +60 3.15 - - V MHz dB dB mV
Operational amplifier (OP4) analog supply voltage 2 gain bandwidth product power supply rejection ratio positive slew rate negative slew rate voltage offset minimum output voltage maximum output voltage output current note 5 CL = 120 pF; VDDA2 = 5 V; note 2 VDDA2 = 5 V, at 217 Hz VDDA2 = 5 V; note 4 VDDA2 = 5 V; note 4 no load at output 2.7 4 50(3) 3.5 3.5 -20 - 0.85VDDA2 4.5 - - DC = 1; DR0 = 1; note 6 DC = 1; DR0 = 0; note 6 DC = 1; DR0 = 1 DC = 1; DR0 = 0 Programmability and accuracy of VKICK (DAC8) at VINT(O) Vo(min) Vo(max) STS minimum output voltage maximum output voltage step size DC = 1; DR0 = 1; note 6 DC = 1; DR0 = 0; note 6 DC = 1; DR0 = 1 DC = 1; DR0 = 0 -50 270 - - - - 2.6 5.0 +50 400 - - mV mV mV mV -30 2.72 - - 5.0 - 55 15 6 0 - - - 1.5 0.2 - - 6 11.7 V MHz dB V/s V/s mV V V mA
Programmability and accuracy of VPL (DAC8) at VINT(O) INL DNL Vo(min) Vo(max) STS integral non-linearity differential non-linearity minimum output voltage maximum output voltage step size LSB LSB mV V mV mV
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
SYMBOL PARAMETER CONDITIONS MIN. TYP.
PCF5077T
MAX.
UNIT
Programmability and accuracy of VHOME (DAC6) at VINT(O) INL DNL Vo(min) Vo(max) STS Notes 1. Pulses of 7 V are allowed for less than 100 ms. 2. Minimum specified frequency at Tamb = 27 C. For Tamb = 85 C a typical value of 4 MHz is specified. 3. Not tested. Guaranteed by design. 4. Slew rates are measured between 10% and 90% of output voltage with a load of approximately 40 pF to ground. 5. Measured with RL = 1.2 k, CL = 80 pF and VDDA2 = 5 V. The voltage drop at the output is less than 20 mV. 6. Referred to VHOME; nominal operating condition, direct control (DC = 1), VHOME programmed to 40. 7. The parameter is measured starting from code 4, due to a saturation effect for the first four codes. integral non-linearity differential non-linearity minimum output voltage maximum output voltage step size note 7 note 7 DVh1 = 0; DVh0 = 0 DVh1 = 0; DVh0 = 0 - - 50 1.95 - 1.0 0.2 - - 33 3 1 170 2.25 - LSB LSB mV V mV
1997 Nov 19
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PCF5077T
DC CHARACTERISTICS VDDA1, VDDA2 and VDDD = VDD = 2.7 to 6.0 V; VDDD = VDDA1 VDDA2; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL VDDD VDDA1 VDDA2 IDD(idle)(tot) ILIL ILIH Ci VIL VIH VOL VOH ILO ILl Ci Zi Vi(p-p) Vi(VS) Band gap Ibias Vref TC tpu bias current (source for D1) reference voltage temperature coefficient for Vref power-up time for Vref note 3 Tamb = 25 C; TC = -4 mV/K VVS = 0 V; Tamb = 25 C; TC = -0.08 A/K Tamb = 25 C 21 1.18 - - 28 1.25 170 5 35 1.32 - 50 A V ppm/K s PARAMETER digital supply voltage analog supply voltage 1 analog supply voltage 2 fCLK13 = 13 MHz; see Fig.5 PD = LOW total idle current on the VDD pins LOW-level input leakage current HIGH-level input leakage current input capacitance LOW-level input voltage HIGH-level input voltage CONDITIONS MIN. 2.7 2.7 2.7 - - -5 -5 - 0 TYP. 3.0 3.0 5.0 9 4 - - 10 - MAX. 6.0 6.0 6.0 18 20 UNIT V V V mA A A A pF V
IDD(oper)(tot) total operating current on the VDD pins
Logic inputs (pins TRIG, STROBE, CLK and DATA) VIL = 0 V VIH = 6 V +5 +5 - VDD 0.4 - +5
0.2VDD V
0.5VDD - IOL = IOH = 3 mA IOL = IOH = 3 mA VDF = 0 to VDD - -5 -5 - fCLK13 = 13 MHz; note 1 note 2 - 0.35 -3.0 - - - 10 5 - -
3-state output (pin DF) LOW-state output voltage HIGH-state output voltage 3-state output leakage current V V A A pF k V 0.7VDD -
Low-swing master clock input (pin CLK13) input leakage current input capacitance input impedance input voltage (peak-to-peak value) +5 - - VDD VDD
Sensor input voltage (pin VS) input voltage at pin VS V
Power-on reset, threshold voltage Vth; see Fig.4 Vth trst Notes 1. An AC coupling with 33 pF is recommended. 2. Tested at nominal working condition (VDDD = VDDA1 = 3 V; VDDA2 = 5 V). AC coupling = 33 pF. 3. The necessary start-up time tON = 200 s (see Fig.3) between PD and TRIG is more than tpu. threshold voltage reset time 1.2 - 1.5 - 1.8 50 V s
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PCF5077T
handbook, halfpage
VDDD Vth t < trst internal reset
t
MGK914
Fig.4 Timing diagram for on-chip reset function.
MGK916
handbook, halfpage
8
IDD (mA)
(1)
6
4
(2)
2
(3)
0 3 4 5 VDD (V) 6
(1) IDDA1.
(2) IDDA2.
(3) IDDD.
Fig.5 Operating current IDD as a function of VDD.
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PCF5077T
TIMING CHARACTERISTICS VDDA1, VDDA2 and VDDD = 2.7 to 6.0 V; VDDD = VDDA1 VDDA2; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Controller timing; see Fig.3 td(TRIG-B) td(B-C) td(TRIG-E) td(E-G) delay from positive TRIG edge to time B = 136Tcy delay from time B to time C = 18Tcy delay from negative TRIG edge to time E = delay from time E to time G = 38Tcy
13 6Tcy
PARAMETER - - - -
MIN.
TYP. s s s s
UNIT
1.0 8.31 1.0 17.54
Serial bus timing; see Fig.6 SERIAL PROGRAMMING CLOCK (PIN CLK) tr tf Tcy tstart tend tsu th rise time fall time clock period - - 100 10 10 - - - - - ns ns ns
ENABLE PROGRAMMING (PIN STROBE) strobe start time to first clock edge strobe end time after last clock edge 0 40 ns ns
REGISTER SERIAL INPUT DATA (PIN DATA) input data to CLK set-up time input data to CLK hold time 20 20 ns ns
handbook, full pagewidth
tsu
Tcy
th
CLK
DATA
MSB
LSB
STROBE tstart tend
MGK913
Fig.6 Serial bus timing diagram.
1997 Nov 19
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Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
APPLICATION INFORMATION Direct power control with ramping function (DC = 1) The circuit offers a useful feature to control power levels close to the saturation region of the external power module. This flexibility consists in the direct control on the power level by setting bit DC to logic 1. In this condition, the external control loop is switched off by disabling the gain path from OP1. The ramping shape of the signal to be transmitted as well as its final level are driven only by the internally generated control signal from the slope generator. In this way transient effects to recover active components from deep saturation are avoided. The relative error on the absolute value of output power is quite limited, as a power amplifier is less sensitive to temperature variation in its saturated region. However, this way of operating may increase the phase error. Increased dynamic range The PCF5077T is able to control a dynamic range of 30 dBm by switching the gain factor of the sensor amplifier and the resolution of DAC8. This range corresponds to a maximum peak-to-peak voltage of 3 V measured at the sensor diode. Figure 7 shows the voltage at the sensor diode (VS) versus the output power (P) of the Power Amplifier (PA) with a directional coupler of 20 dB attenuation. The maximum voltage of 3 V is reached when the output power is 35 dBm. The sensor voltage for power level lower than 13 dBm, as necessary for GSM Phase 2 and DCS1800, is lower than 200 mV. An 8-bit DAC would not be sufficient to cover the complete dynamic range. Therefore bits DR0 and DR1 are used to switch the power range that can be controlled with the controller (see Table 7). REDUCED VOLTAGE STEPS OF POWER LEVEL DAC8 (DR0 = 1) The DR0 bit is used to switch resistor R9 (switch DR0 is closed) at the integrator input (OP4). The ratio of the DAC8 range to the sensor signal voltage is therefore halved and the power corresponding to one LSB of DAC8 is reduced by 3 dB. With this setting the power module can be controlled more accurately for low output power levels. GAIN FACTOR OF OP1 (DR1) Bit DR1 switches (switch DR1 is closed) the ratio of the capacitances at OP1. The gain factor for the sensor amplifier is five times higher when DR1 is in high state. 1997 Nov 19 15
PCF5077T
When DR1 = 1, the control loop regulates the output power of the PA to a lower power level. A dynamic range of about 10 dBm can be switched by this manner. Vs : Vpeak is the ratio of sensor signal to slope generator output voltage effective at the integrator output (OP4). Table 7 Gain factors DR0 0 1 0 1 VS : Vpeak 1:1 2:1 5:1 10 : 1
DR1 0 0 1 1
Additional application information Evaluation kits with software and demonstration board are available for the PCF5077T together with Philips power modules BGY206, CGY2010, CGY2020 and CGY2021 for GSM and PCN, which will provide help for applications. Very little bus traffic is required for the PCF5077T because the ramping curves are generated on-chip. VKICK and VHOME define the start conditions for up-ramping. VPL determines the power levels. TRIG is the trigger for up and down-ramping. The non-linear behaviour of the control curves of the power modules have a big influence on the loop. Start conditions in the flat area of the control curve are critical and need some attention. Initially VINT(O) will be at the home position. The HPA switches release the regulator. The integrator is moved into the active part of the control curve. This is achieved by integrating VKICK. When VINT(O) has reached the active region of the control curve the loop is closed and the circuit is able to follow the ramping function generated by a voltage step to the slope generator. The step height VPL determines the power of the transmit burst. Down-ramping is started at the slope generator input by a voltage step from VPL back to VQRS. The loop follows the leading function for down-ramping until the RF sensor measures zero. The reason for VQRS is to shorten the tail of the slope. Figures 8 and 9 show the results of measurements on the up and down-ramping where REF is the reference level of the power in the time slot, ATTEN is the attenuation of the input instrument for not to destroy the instrument itself, RES BW is the resolution bandwidth, VBW is the video bandwidth, CENTER is the carrier frequency for the burst that has been measured and SWP is the sweep time used for the measurement.
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
ADJUSTMENT OF THE HOME POSITION The 6-bit DAC for VHOME determines the start point of the burst in the time template. Curve 2 in Fig.8 shows what happens when VHOME is too low. The burst starts too late and the up-ramping of the power is too steep. The steep up-ramping results in a wide transient spectra. The RF input power shall be switched off when the TRIG signal is LOW to keep the -70 dB margin before the burst. The home position has to be adjusted for each mobile phone because of DAC tolerances and individual PA characteristics. The temperature coefficients for VHOME (-2 and -4 mV/K) are used to compensate the temperature shift of the PA control curve. Therefore the PA and the controller shall be placed nearby on the printed-circuit board. Additionally it has to be considered that the temperature of the PA and PCF5077T are different because the PA heats up itself. Software may help to adapt VHOME to different temperatures. ADJUSTMENT OF VKICK After the falling edge of HPA the integrator starts to increase the control voltage up to the position of VKICK where the PA should have reached its active region. Increasing VKICK at high power level makes the up ramping of the burst smoother and improves the transient spectra.
PCF5077T
VKICK must be reduced for low level of VPL to avoid that both voltages become equal. Setting VKICK to minimum value for the lowest power level can be sufficient. At low power level the burst will start later because of the bend sensor curve (see Fig.7). The trigger pulse has to be started up to 3 bits earlier for the lowest power level to avoid that the power is ramped up too late for the first data bits of the burst. LIMIT FOR CORRECT DOWN-RAMPING The maximum RF power that the power module in saturation is able to deliver depends on RF input power, transmit frequency, supply voltage, temperature and load impedance. The maximum VPL must be matched to the worst case output power and then reduced by 1 dB when the PCF5077T is used in closed loop mode. Curve 2 in Fig.9 shows what happens when the PA is driven into saturation. The down-ramping of the power is getting too steep and therefore the transient spectra will be too wide. The 1 dB margin is necessary because of the flat PA control curve at high power level. The loop needs more time to reduce the power during the down-ramping and the control voltage increases. The high control voltage forces the power quickly down when the steep region of the control curve is achieved. The steep down-ramping results in a wide transient spectra.
handbook, halfpage
10
MGK915
VS (V) 1
10-1
10-2 -5
0
5
10
15
20
25
30 35 P (dBm)
Fig.7 Sensor voltage as a function of output power (diode BAT62).
1997 Nov 19
16
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PCF5077T
REF 33.4 dBm
handbook, full pagewidth
ATTEN 40 dB 6 dB
+4 dB
+1 dB 1 dB
MBE718
LOG 10 dB/
30 dB
KICK
1
2
70 dB
40 CENTER 902.400 MHz # RES BW 300 kHz
28
18
10
0 s
32 # SWP 80 s
# VBW 300 kHz
(1) Highest usable value. (2) Lowest usable value.
Fig.8 Power as a function of time; rising edge (behaviour at different worst case home positions of VINT(O)).
handbook, full pagewidth
REF 34.8 dBm LOG 10 dB/
ATTEN 40 dB
MBE719
1
2
6 dB
30 dB
70 dB
543 s CENTER 902.400 MHz # RES BW 1.0 MHz
553
561
571
591 # SWP 80 s
# VBW 300 kHz
(1) Correct behaviour. (2) Unusable behaviour with wrong VPL value.
Fig.9 Power as a function of time; falling edge.
1997 Nov 19
17
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
Application in mobile stations Using a directional coupler with 16.5 dB attenuation produces a sensor signal between 100 mV and 3 V below the diode forward voltage at pin VS for the PA output power range of 8 to 36 dBm.
PCF5077T
The sensor voltage of 3 V at pin VS corresponds to the maximum DAC output voltage. The power range that can be controlled is therefore not limited by the sensor voltage input VS and higher power levels can be controlled with the control loop switched on.
handbook, full pagewidth
antenna sensor C2 8.2 to 39 pF R1 1 k VS 1 2 3 4 TRIG 16 15 14 13 VINT(N) VINT(O) VSSA VSSD DATA CLK STROBE 3-wire serial bus C1 120 pF RF POWER AMPLIFIER
RF
D1
PCF5077T
5 6 12 11 10 9
PD C3 33 pF CLK13
7 8
MGK911
Fig.10 Application diagram for mobile stations.
1997 Nov 19
18
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
PCF5077T
SOT369-1
D
E
A X
c y HE vM A
Z
16
9
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-04-20 95-02-04
1997 Nov 19
19
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
PCF5077T
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Nov 19
20
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF5077T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Nov 19
21
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
NOTES
PCF5077T
1997 Nov 19
22
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
NOTES
PCF5077T
1997 Nov 19
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/1200/01/pp24
Date of release: 1997 Nov 19
Document order number:
9397 750 02733

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